User's Manual

I2S protocol is “I2S Justified” as shown below.
Note 1: The timing specified for the rise and fall times represents the edge rates on the module itself. The rise and
fall times of the I2S signals are determined by ESD/EMI mitigation components on the modules, as well as external
loading, and will be higher than the specified numbers
6.10 I2C Master/Slave Communication Interface Timing (S_SCL, S_SDA)
The SWA51 has both I2C slave and master interfaces available with their respective pins S_SCL, S_SDA and
M_SCL, M_SDA. The interfaces operate in I2C fast-mode and can receive and transmit at up to 400 kbit/s.
Bytes are 8 bits long and are transferred with the most significant bit (MSB) first. Each byte has to be followed by an
acknowledge bit. The SWA51 will apply clock-stopping (by holding the clock line S_SCL LOW to force the master
into a wait state) if necessary due to internal high-priority tasks.
The slave/master interface can be used both for writing (e.g. sending commands) or reading (e.g. requesting status).
An additional GPIO pin on the SWA51 (Ex. GPIO24), can be used to notify the I2C master when a pending message
is ready to be sent.
The SWA51 slave interface responds to the 7-bit slave address 1000000 (0x40) as shown in Figure 1 below.
Figure 5: First Byte after the START Procedure
ELECTRICAL SPECIFICATIONS AND TIMING
Table 3: Characteristics of the S_SDA and S_SCL I/Os
PARAMETER SYMBOL
FAST-MODE
UNIT
MIN. MAX.
LOW level input voltage VIL 0.3ˢ 0.8 V
HIGH level input voltage VIH 2.0 3.6 V
LOW level output voltage (open drain or
open collector) at 1 mA sink current:
VOL 0 0.4 V
Output fall time from VIHmin to VILmax with
a bus capacitance from 10 pF to 400 pF
tof 0 250 ns