Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 99
© 2012 Broadcom Corporation. All rights reserved
GPIO Low Detect Enable Registers (GPLENn)
S
YNOPSIS The low level detect enable registers define the pins for which a low level sets a bit in
the event detect status register (GPEDSn). If the pin is still low when an attempt is
made to clear the status bit in GPEDSn then the status bit will remain set.
Bit(s) Field Name Description Type Reset
31-0 LENn (n=0..31)
0 =
Low
detect disabled on GPIO pin
n
1 = Low on GPIO pin n sets corresponding bit in GPEDS
R/W 0
Table 6-22 – GPIO Low Detect Status Register 0
Bit(s) Field Name Description Type Reset
31-22 -
Reserved
R 0
21-0 LENn (n=32..53)
0 =
Low
detect disabled on GPIO pin
n
1 = Low on GPIO pin n sets corresponding bit in GPEDS
R/W 0
Table 6-23 – GPIO Low Detect Status Register 1
GPIO Asynchronous rising Edge Detect Enable Registers (GPARENn)
S
YNOPSIS The asynchronous rising edge detect enable registers define the pins for which a
asynchronous rising edge transition sets a bit in the event detect status registers
(GPEDSn).
Asynchronous means the incoming signal is not sampled by the system clock. As such
rising edges of very short duration can be detected.
Bit(s) Field Name Description Type Reset
31-0 ARENn (n=0..31)
0 = Asynchronous rising edge detect disabled on GPIO pin
n.
1 = Asynchronous rising edge on GPIO pin n sets
corresponding bit in EDSn.
R/W 0
Table 6-24 – GPIO Asynchronous rising Edge Detect Status Register 0
Bit(s) Field Name Description Type Reset
31-22 -
Reserved
R 0
21-0 ARENn
(n=32..53)
0 = Asynchronous rising edge detect disabled on GPIO pin
n.
1 = Asynchronous rising edge on GPIO pin n sets
corresponding bit in EDSn.
R/W 0