Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 9
© 2012 Broadcom Corporation. All rights reserved
0x7E21 50C8 AUX_SPI1_STAT_REG SPI 2 Status 32
0x7E21 50D0 AUX_SPI1_IO_REG SPI 2 Data 32
0x7E21 50D4 AUX_SPI1_PEEK_REG SPI 2 Peek 16
2.1.1 AUX registers
There are two Auxiliary registers which control all three devices. One is the interrupt status
register, the second is the Auxiliary enable register. The Auxiliary IRQ status register can
help to hierarchically determine the source of an interrupt.
AUXIRQ Register (0x7E21 5000)
S
YNOPSIS The AUXIRQ register is used to check any pending interrupts which may be asserted by
the three Auxiliary sub blocks.
Bit(s) Field Name Description Type Reset
31:3
Reserved, write zero, read as don’t care
2
SPI 2 IRQ If set the SPI 2 module has an interrupt pending. R 0
1
SPI 1 IRQ If set the SPI1 module has an interrupt pending. R 0
0
Mini UART
IRQ
If set the mini UART has an interrupt pending. R 0
AUXENB Register (0x7E21 5004)
S
YNOPSIS The AUXENB register is used to enable the three modules; UART, SPI1, SPI2.
Bit(s) Field Name Description Type Reset
31:3
Reserved, write zero, read as don’t care
2
SPI2 enable If set the SPI 2 module is enabled.
If clear the SPI 2 module is disabled. That also
disables any SPI 2 module register access
R/W 0
1
SPI 1 enable If set the SPI 1 module is enabled.
If clear the SPI 1 module is disabled. That also
disables any SPI 1 module register access
R/W 0
0
Mini UART
enable
If set the mini UART is enabled. The UART will
immediately start receiving data, especially if the
UART1_RX line is low.
If clear the mini UART is disabled. That also disables
any mini UART register access
R/W 0