Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 87
© 2012 Broadcom Corporation. All rights reserved
Synopsis
This register is used to delay the card clock when sampling the returning data and
command response from the card. It determines by how many steps the sampling
clock is delayed in DDR mode.
Bit(s)
Field
Name
Description
Type
Reset
31:6
Reserved
-
Write as 0, read as don't care
5:0 STEPS Number of steps (0 to 40) RW 0x0
SPI_INT_SPT Register
Synopsis
This register controls whether assertion of interrupts in SPI mode is possible
independent of the card select line.
For the exact details please refer to the Arasan documentation
SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bit marked as
reserved in this document but not by the Arasan documentation refer to functionality
which has been disabled due to the changes listed in the previous chapter.
Bit(s)
Field Name
Description
Type
Reset
31:8
Reserved
-
Write as 0, read as don't care
7:0 SELECT Interrupt independent of card select line:
0 = no
1 = yes
RW 0x0
SLOTISR_VER Register
Synopsis
This register contains the version information and slot interrupt status.
For the exact details please refer to the Arasan documentation
SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bit marked as
reserved in this document but not by the Arasan documentation refer to functionality
which has been disabled due to the changes listed in the previous chapter.
Bit(s)
Field Name
Description
Type
Reset
31:24 VENDOR Vendor Version Number RW 0x0
23:16 SDVERSION Host Controller specification version RW 0x0