Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 86
© 2012 Broadcom Corporation. All rights reserved
0 ENABLE Enable the extension FIFO:
0 = bypass
1 = enabled
RW 0x0
TUNE_STEP Register
Synopsis
This register is used to delay the card clock when sampling the returning data and
command response from the card.
DELAY determines by how much the sampling clock is delayed per step.
Bit(s)
Field Name
Description
Type
Reset
31:3
Reserved
-
Write as 0, read as don't care
2:0 DELAY Sampling clock delay per step:
000 = 200ps typically
001 = 400ps typically
010 = 400ps typically
011 = 600ps typically
100 = 700ps typically
101 = 900ps typically
110 = 900ps typically
111 = 1100ps typically
RW 0x0
TUNE_STEPS_STD Register
Synopsis
This register is used to delay the card clock when sampling the returning data and
command response from the card. It determines by how many steps the sampling
clock is delayed in SDR mode.
Bit(s)
Field Name
Description
Type
Reset
31:6
Reserved
-
Write as 0, read as don't care
5:0 STEPS Number of steps (0 to 40) RW 0x0
TUNE_STEPS_DDR Register