Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 77
© 2012 Broadcom Corporation. All rights reserved
5 READ_RDY DATA register contains data to be read:
0 = no
1 = yes
RW 0x0
4 WRITE_RDY Data can be written to DATA register:
0 = no
1 = yes
RW 0x0
3
Reserved
-
Write as 0, read as don't care
2 BLOCK_GAP Data transfer has stopped at block gap:
0 = no
1 = yes
RW 0x0
1 DATA_DONE Data transfer has finished:
0 = no
1 = yes
RW 0x0
0 CMD_DONE Command has finished:
0 = no
1 = yes
RW 0x0
IRPT_MASK Register
Synopsis
This register is used to mask the interrupt flags in the INTERRUPT register.
For the exact details please refer to the Arasan documentation
SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as
reserved in this document but not by the Arasan documentation refer to functionality
which has been disabled due to the changes listed in the previous chapter.
Bit(s)
Field Name
Description
Type
Reset
31:25
Reserved
-
Write as 0, read as don't care
24 ACMD_ERR Set flag if auto command error:
0 = no
1 = yes
RW 0x0
23
Reserved
-
Write as 0, read as don't care
22 DEND_ERR Set flag if end bit on data line not 1:
0 = no
1 = yes
RW 0x0