Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 75
© 2012 Broadcom Corporation. All rights reserved
7:6 CLK_FREQ_MS2 SD clock base divider MSBs RW 0x0
5 CLK_GENSEL Mode of clock generation:
0 = divided
1 = programmable
RW 0x0
4:3
Reserved
-
Write as 0, read as don't care
2 CLK_EN SD clock enable:
0 = disabled
1 = enabled
RW 0x0
1 CLK_STABLE SD clock stable:
0 = no
1 = yes
RO 0x0
0 CLK_INTLEN Clock enable for internal EMMC clocks for power
saving:
0 = disabled
1 = enabled
RW 0x0
INTERRUPT Register
Synopsis
This register holds the interrupt flags. Each flag can be disabled using the according bit
in the IRPT_MASK register.
For the exact details please refer to the Arasan documentation
SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as
reserved in this document but not by the Arasan documentation refer to functionality
which has been disabled due to the changes listed in the previous chapter.
ERR is a generic flag and is set if any of the enabled error flags is set.
Bit(s)
Field Name
Description
Type
Reset
31:25
Reserved
-
Write as 0, read as don't care
24 ACMD_ERR Auto command error:
0 = no error
1 = error
RW 0x0
23
Reserved
-
Write as 0, read as don't care
22 DEND_ERR End bit on data line not 1:
0 = no error
1 = error
RW 0x0