Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 74
© 2012 Broadcom Corporation. All rights reserved
4:3
Reserved
-
Write as 0, read as don't care
2 HCTL_HS_EN Select high speed mode (i.e. DAT and CMD
lines change on the rising CLK edge):
0 = disabled
1 = enabled
RW 0x0
1 HCTL_DWIDTH Use 4 data lines:
0 = disabled
1 = enabled
RW 0x0
0
Reserved
-
Write as 0, read as don't care
CONTROL1 Register
Synopsis
This register is used to configure the EMMC module.
For the exact details please refer to the Arasan documentation
SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as
reserved in this document but not by the Arasan documentation refer to functionality
which has been disabled due to the changes listed in the previous chapter.
CLK_STABLE seems contrary to its name only to indicate that there was a rising edge
on the clk_emmc input but not that the frequency of this clock is actually stable.
Bit(s)
Field Name
Description
Type
Reset
31:27
Reserved
-
Write as 0, read as don't care
26 SRST_DATA Reset the data handling circuit:
0 = disabled
1 = enabled
RW 0x0
25 SRST_CMD Reset the command handling circuit:
0 = disabled
1 = enabled
RW 0x0
24 SRST_HC Reset the complete host circuit:
0 = disabled
1 = enabled
RW 0x0
23:20
Reserved
-
Write as 0, read as don't care
19:16 DATA_TOUNIT Data timeout unit exponent:
1111 = disabled
x = TMCLK * 2^(x+13)
RW 0x0
15:8 CLK_FREQ8 SD clock base divider LSBs RW 0x0