Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 73
© 2012 Broadcom Corporation. All rights reserved
CONTROL0 Register
Synopsis
This register is used to configure the EMMC module.
For the exact details please refer to the Arasan documentation
SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as
reserved in this document but not by the Arasan documentation refer to functionality
which has been disabled due to the changes listed in the previous chapter.
Bit(s)
Field Name
Description
Type
Reset
31:23
Reserved
-
Write as 0, read as don't care
22 ALT_BOOT_EN Enable alternate boot mode access:
0 = disabled
1 = enabled
RW 0x0
21 BOOT_EN Boot mode access:
0 = stop boot mode access
1 = start boot mode access
RW 0x0
20 SPI_MODE SPI mode enable:
0 = normal mode
1 = SPI mode
RW 0x0
19 GAP_IEN Enable SDIO interrupt at block gap (only valid if
the HCTL_DWIDTH bit is set):
0 = disabled
1 = enabled
RW 0x0
18 READWAIT_EN Use DAT2 read-wait protocol for SDIO cards
supporting this:
0 = disabled
1 = enabled
RW 0x0
17 GAP_RESTART Restart a transaction which was stopped using
the GAP_STOP bit:
0 = ignore
1 = restart
RW 0x0
16 GAP_STOP Stop the current transaction at the next block
gap:
0 = ignore
1 = stop
RW 0x0
15:6
Reserved
-
Write as 0, read as don't care
5 HCTL_8BIT Use 8 data lines:
0 = disabled
1 = enabled
RW 0x0