Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 72

STATUS Register

Synopsis

This register contains information intended for debugging. Its values change

automatically according to the hardware. As it involves resynchronisation between

different clock domains it changes only after some latency and it is easy sample the

values too early.

Therefore it is not recommended to use this register for polling. Instead use the

INTERRUPT register which implements a handshake mechanism which makes it

impossible to miss a change when polling.

Bit(s)

Field Name

Description

Type

Reset

31:29

Reserved

Write as 0, read as don't care

28:25 DAT_LEVEL1 Value of data lines DAT7 to DAT4 RW 0xf

24 CMD_LEVEL Value of command line CMD RW 0x1

23:20 DAT_LEVEL0 Value of data lines DAT3 to DAT0 RW 0xf

19:10

Reserved

Write as 0, read as don't care

9 READ_TRANSFER New data can be read from EMMC:

0 = no

1 = yes

RW 0x0

8 WRITE_TRANSFER New data can be written to EMMC:

0 = no

1 = yes

RW 0x0

7:3

Reserved

Write as 0, read as don't care

2 DAT_ACTIVE At least one data line is active:

0 = no

1 = yes

RW 0x0

1 DAT_INHIBIT Data lines still used by previous data transfer:

0 = no

1 = yes

RW 0x0

0 CMD_INHIBIT Command line still used by previous command:

0 = no

1 = yes

RW 0x0