Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 67
© 2012 Broadcom Corporation. All rights reserved
0x18
RESP2
Response bits 95 : 64 32
0x1c
RESP3
Response bits 127 : 96 32
0x20
DATA
Data 32
0x24
STATUS
Status 32
0x28
CONTROL0
Host Configuration bits 32
0x2c
CONTROL1
Host Configuration bits 32
0x30
INTERRUPT
Interrupt Flags 32
0x34
IRPT_MASK
Interrupt Flag Enable 32
0x38
IRPT_EN
Interrupt Generation Enable 32
0x3c
CONTROL2
Host Configuration bits 32
0x50
FORCE_IRPT
Force Interrupt Event 32
0x70
BOOT_TIMEOUT
Timeout in boot mode 32
0x74
DBG_SEL
Debug Bus Configuration 32
0x80
EXRDFIFO_CFG
Extension FIFO Configuration 32
0x84
EXRDFIFO_EN
Extension FIFO Enable 32
0x88
TUNE_STEP
Delay per card clock tuning step 32
0x8c
TUNE_STEPS_STD
Card clock tuning steps for SDR 32
0x90
TUNE_STEPS_DDR
Card clock tuning steps for DDR 32
0xf0
SPI_INT_SPT
SPI Interrupt Support 32
0xfc
SLOTISR_VER
Slot Interrupt Status and Version 32
ARG2 Register