Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 66

The software is responsible for checking the status bits of the card’s response in order to

verify successful processing by the card.

In order to transfer data from/to the card register DATA is accessed after configuring the host

and sending the according commands to the card using CMDTM. Because the EMMC

module doesn’t interpret the commands sent to the card it is important to configure it

identical to the card setup using the CONTROL0 register. Especial care should be taken to

make sure that the width of the data bus is configured identical for host and card. The card is

synchronized to the data flow by switching off its clock appropriately. A handshake signal

dma_req is available for paced data transfers. Bit 1 of the INTERRUPT register can used to

determine whether a data transfer has finished. Please note that the INTERRUPT register is

not self clearing, so the software has first to reset it by writing 1 before using it to detect if a

data transfer has finished.

The EMMC module restricts the maximum block size to the size of the internal data FIFO

which is 1k bytes. In order to get maximum performance for data transfers it is necessary to

use multiple block data transfers. In this case the EMMC module uses two FIFOs in ping-

pong mode, i.e. one is used to transfer data to/from the card while the other is simultaneously

accessed by DMA via the AXI bus. If the EMMC module is configured for single block

transfers only one FIFO is used, so no DMA access is possible while data is transferred

to/from the card and vice versa resulting in long dead times.

o Registers

Contrary to Arasan™’s documentation the EMMC module registers can only be accessed as

32 bit registers, i.e. the two LSBs of the address are always zero.

The EMMC register base address is 0x7E300000

EMMC Address Map

Address

Offset

0x0

ARG2

ACMD23 Argument 32

0x4

BLKSIZECNT

Block Size and Count 32

0x8

ARG1

Argument 32

0xc

MDTM

Command and Transfer Mode 32

0x10

RESP0

Response bits 31 : 0 32

0x14

RESP1

Response bits 63 : 32 32