Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 65

5 External Mass Media Controller

o Introduction

The External Mass Media Controller (EMMC) is an embedded MultiMedia™ and SD™ card

interface provided by Arasan™. It is compliant to the following standards:

• SD™ Host Controller Standard Specification Version 3.0 Draft 1.0

• SDIO™ card specification version 3.0

• SD™ Memory Card Specification Draft version 3.0

• SD™ Memory Card Security Specification version 1.01

• MMC™ Specification version 3.31,4.2 and 4.4

For convenience in the following text card is used as a placeholder for SD™, embedded

MultiMedia and SDIO™ cards.

For detailed information about the EMMC internals please refer to the Arasan™ document

SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf but make sure to read the

following chapter which lists the changes made to Arasan™’s IP.

Because the EMMC module shares pins with other functionality it must be selected in the

GPIO interface. Please refer to the GPIO section for further details.

The interface to the card uses its own clock clk_emmc which is provided by the clock

manager module. The frequency of this clock should be selected between 50 MHz and 100

MHz. Having a separate clock allows high performance access to the card even if the

VideoCore runs at a reduced clock frequency. The EMMC module contains its own internal

clock divider to generate the card’s clock from clk_emmc.

Additionally can the sampling clock for the response and data from the card be delayed in up

to 40 steps with a configurable delay between 200ps to 1100ps per step typically. The delay

is intended to cancel the internal delay inside the card (up to 14ns) when reading. The delay

per step will vary with temperature and supply voltage. Therefore it is better to use a bigger

delay than necessary as there is no restriction for the maximum delay.

The EMMC module handles the handshaking process on the command and data lines and all

CRC processing automatically.

Command execution is commenced by writing the command plus the appropriate flags to the

CMDTM register after loading any required argument into the ARG1 register. The EMMC

module calculates the CRC checksum, transfers the command to the card, receives the

response and checks its CRC. Once the command has executed or timed-out bit 0 of register

INTERRUPT will be set. Please note that the INTERRUPT register is not self clearing, so the

software has first to reset it by writing 1 before using it to detect if a command has finished.