Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 63

4.3 AXI Bursts

The DMA supports bursts under specific conditions. Up to 16 beat bursts can be

accommodated.

Peripheral (32 bit wide) read bursts are supported. The DMA will generate the burst if there

is sufficient room in its read buffer to accommodate all the data from the burst. This limits the

burst size to a maximum of 8 beats.

Read bursts in destination ignore mode (DEST_IGNORE) are supported as there is no need

for the DMA to deal with the data. This allows wide bursts of up to 16 beats to be used for

efficient L2 cache fills.

DMA channel 0 and 15 are fitted with an external 128 bit 8 word read FIFO. This enables

efficient memory to memory transfers to be performed. This FIFO allows the DMA to

accommodate a wide read burst up to the size of the FIFO. In practice this will allow a 128

bit wide read burst of 9 as the first word back will be immediately read into the DMA engine

(or a 32 bit peripheral read burst of 16 – 8 in the input buffer and 8 in the fifo). On any DMA

channel, if a read burst is selected that is too large, the AXI read bus will be stalled until the

DMA has written out the data. This may lead to inefficient system operation, and possibly

AXI lock up if it causes a circular dependancy.

In general write bursts are not supported. However to increase the efficiency of L2 cache

fills, src_ignore (SRC_IGNORE) transfers can be specified with a write burst. In this case

the DMA will issue a write burst address sequence followed by the appropriate number of

zero data, zero strobe write bus cycles, which will cause the cache to pre-fetch the data. To

improve the efficiency of the 128 bit wide bus architecture, and to make use of the DMAs

internal 256 bit registers, the DMA will generate 128 bit wide writes as 2 beat bursts

wherever possible, although this behaviour can be disabled.

4.4 Error Handling

If the DMA detects a Read Response error it will record the fact in the READ_ERROR flag

in the debug register. This will remain set until it is cleared by writing a 1 to it. The DMA

will clear its active flag and generate an interrupt. Any outstanding read data transactions

(remainder of a burst) will be honoured. This allows the operator to either restart the DMA

by clearing the error bit and setting the active bit, or to abort the DMA transfer by clearing

the NEXTCONBK register and restarting the DMA with the ABORT bit set.

The DMA will also record any errors from an external read FIFO. These will be latched in

the FIFO_ERROR bit in the debug register until they are cleared by writing a ‘1’ to the bit.

(note that only DMA0 and 15 have an external read fifo)

If the DMA detects that a read occurred without the AXI rlast set as expected then it will set

the READ_LAST_NOT_SET_ERROR bit in the debug register. This can be cleared by

writing a ‘1’ to it.

The error bits are logically OR’d together and presented as a general ERROR bit in the CS

4.5 DMA LITE Engines

Several of the DMA engines are of the LITE design. This is a reduced specification engine

designed to save space. The engine behaves in the same way as a normal DMA engine

except for the following differences.