Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 61

4.2.1.3 Peripheral DREQ Signals

A DREQ (Data Request) mechanism is used to pace the data flow between the DMA and a

peripheral.

Each peripheral is allocated a permanent DREQ signal. Each DMA channel can select which

of the DREQ signals should be used to pace the transfer by controlling the DMA reads, DMA

writes or both. Note that DREQ 0 is permanently enabled and can be used if no DREQ is

required.

When a DREQ signal is being used to pace the DMA reads, the DMA will wait until it has

sampled DREQ high before launching a single or burst read operation. It will then wait for all

the read data to be returned before re-checking the DREQ and starting the next read. Thus

once a peripheral receives the read request it should remove its DREQ as soon as possible to

prevent the DMA from re-sampling the same DREQ assertion.

DREQ’s are not required when reading from AXI peripherals. In this case, the DMA will

request data from the peripheral and the peripheral will only send the data when it is

available. The DMA will not request data that is does not have room for, so no pacing of the

data flow is required.

DREQ’s are required when reading from APB peripherals as the AXI-to-APB bridge will not

wait for an APB peripheral to be ready and will just perfom the APB read regardless. Thus

an APB peripheral needs to make sure that it has all of its read data ready before it drives its

DREQ high.

When writing to peripherals, a DREQ is always required to pace the data. However, due to

the pipelined nature of the AXI bus system, several writes may be in flight before the

peripheral receives any data and withdraws its DREQ signal. Thus the peripheral must

ensure that it has sufficient room in its input FIFO to accommodate the maximum amount of

data that it might receive. If the peripheral is unable to do this, the DMA WAIT_RESP

mechanism can be used to ensure that only one write is in flight at any one time, however this

is less efficient transfer mechanism.

The mapping of peripherals to DREQ’s is as follows:

DREQ

Peripheral

DREQ = 1

This is always on so use this

channel if no DREQ is required.

DSI

PCM TX

PCM RX

SMI

PWM

SPI TX

SPI RX