Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 59
© 2012 Broadcom Corporation. All rights reserved
31:16
Reserved
-
Write as 0, read as don't care
15
INT15
Interrupt status of DMA engine 15
RW
0x0
14
INT14
Interrupt status of
DMA engine 14
RW
0x0
13
INT13
Interrupt status of DMA engine 13
RW
0x0
12
INT12
Interrupt status of DMA engine 12
RW
0x0
11
INT11
Interrupt status of DMA engine 11
RW
0x0
10
INT10
Interrupt status of DMA engine 10
RW
0x0
9
INT9
Interrupt status of
DMA engine 9
RW
0x0
8
INT8
Interrupt status of DMA engine 8
RW
0x0
7
INT7
Interrupt status of DMA engine 7
RW
0x0
6
INT6
Interrupt status of DMA engine 6
RW
0x0
5
INT5
Interrupt status of DMA engine 5
RW
0x0
4
INT4
Interrupt status of DMA engine 4
RW
0x0
3
INT3
Interrupt status of DMA engine 3
RW
0x0
2
INT2
Interrupt status of DMA engine 2
RW
0x0
1
INT1
Interrupt status of DMA engine 1
RW
0x0
0
INT0
Interrupt status of DMA engine 0
RW
0x0
ENABLE Register
Synopsis
Global enable bits for each
channel
Bit(s)
Field Name
Description
Type
Reset
31:15
Reserved
-
Write as 0, read as don't care