Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 57
© 2012 Broadcom Corporation. All rights reserved
4
DEST_INC
Destination Address Increment
1 = Destination address increments after each write
The address will increment by 4, if DEST_WIDTH=0
else by 32.
0 = Destination address does not change.
RW
0x0
3
WAIT_RESP
Wait for a Write Response
When set this makes the DMA wait until it receives
the AXI write response for each write. This ensures
that multiple writes cannot get stacked in the AXI bus
pipeline.
1= Wait for the write response to be received before
proceeding.
0 = Don t wait; continue as soon as the write data is
sent.
RW
0x0
2:1
Reserved
-
Write as 0, read as don't care
0
INTEN
Interrupt Enable
1 = Generate an interrupt when the transfer described
by the current Control Block completes.
0 = Do not generate an interrupt.
RW
0x0
7_TXFR_LEN 8_TXFR_LEN 9_TXFR_LEN 10_TXFR_LEN 11_TXFR_LEN 12_TXFR_LEN 13_TXFR_LEN
14_TXFR_LEN Register
Synopsis
DMA Transfer Length
Bit(s)
Field Name
Description
Type
Reset
31:16
Reserved
-
Write as 0, read as don't care
15:0
XLENGTH
Transfer Length
Length of transfer, in bytes. Updated by the DMA
engine as the transfer progresses.
RW
0x0
7_DEBUG 8_DEBUG 9_DEBUG 10_DEBUG 11_DEBUG 12_DEBUG 13_DEBUG 14_DEBUG Register
Synopsis
DMA Lite Debug register.
Bit(s)
Field Name
Description
Type
Reset