Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 56
© 2012 Broadcom Corporation. All rights reserved
25:21
WAITS
Add Wait Cycles
This slows down the DMA throughput by setting the
number of dummy cycles burnt after each DMA read
or write operation is completed.
A value of 0 means that no wait cycles are to be
added.
RW
0x0
20:16
PERMAP
Peripheral Mapping
Indicates the peripheral number (1-31) whose ready
signal shall be used to control the rate of the
transfers, and whose panic signals will be output on
the DMA AXI bus. Set to 0 for a continuous un-paced
transfer.
RW
0x0
15:12
BURST_LENGTH
Burst Transfer Length
Indicates the burst length of the DMA transfers. The
DMA will attempt to transfer data as bursts of this
number of words. A value of zero will produce a single
transfer. Bursts are only produced for specific
conditions, see main text.
RW
0x0
11
SRC_IGNORE
RW
0x0
10
SRC_DREQ
Control Source Reads with DREQ
1 = The DREQ selected by PER_MAP will gate the
source reads.
0 = DREQ has no effect.
RW
0x0
9
SRC_WIDTH
Source Transfer Width
1 = Use 128-bit source read width.
0 = Use 32-bit source read width.
RW
0x0
8
SRC_INC
Source Address Increment
1 = Source address increments after each read. The
address will increment by 4, if S_WIDTH=0 else by 32.
0 = Source address does not change.
RW
0x0
7
DEST_IGNORE
RW
0x0
6
DEST_DREQ
Control Destination Writes with DREQ
1 = The DREQ selected by PERMAP will gate the
destination writes.
0 = DREQ has no effect.
RW
0x0
5
DEST_WIDTH
Destination Transfer Width
1 = Use 128-bit destination write width.
0 = Use 32-bit destination write width.
RW
0x0