Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 52
© 2012 Broadcom Corporation. All rights reserved
7
DEST_IGNORE
Ignore Writes
1 = Do not perform destination writes.
0 = Write data to destination.
RW
0x0
6
DEST_DREQ
Control Destination
Writes with DREQ
1 = The DREQ selected by PERMAP will gate the
destination writes.
0 = DREQ has no effect.
RW
0x0
5
DEST_WIDTH
Destination Transfer Width
1 = Use 128-bit destination write width.
0 = Use 32-bit destination write width.
RW
0x0
4
DEST_INC
Destination Address Increment
1 = Destination address increments after each write
The address will increment by 4, if DEST_WIDTH=0
else by 32.
0 = Destination address does not change.
RW
0x0
3
WAIT_RESP
Wait for a Write Response
When set this makes the DMA wait until it receives
the AXI write response for each write. This ensures
that multiple writes cannot get stacked in the AXI bus
pipeline.
1= Wait for the write response to be received before
proceeding.
0 = Don t wait; continue as soon as the write data is
sent.
RW
0x0
2
Reserved
-
Write as 0, read as don't care
1
TDMODE
2D Mode
1 = 2D mode interpret the TXFR_LEN register as
YLENGTH number of transfers each of XLENGTH, and
add the strides to the address after each transfer.
0 = Linear mode interpret the TXFR register as a single
transfer of total length {YLENGTH ,XLENGTH}.
RW
0x0
0
INTEN
Interrupt Enable
1 = Generate an interrupt when the transfer described
by the current Control Block completes.
0 = Do not generate an interrupt.
RW
0x0
0_SOURCE_AD 1_SOURCE_AD 2_SOURCE_AD 3_SOURCE_AD 4_SOURCE_AD 5_SOURCE_AD
6_SOURCE_AD 7_SOURCE_AD 8_SOURCE_AD 9_SOURCE_AD 10_SOURCE_AD 11_SOURCE_AD
12_SOURCE_AD 13_SOURCE_AD 14_SOURCE_AD Register