Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 50
© 2012 Broadcom Corporation. All rights reserved
1
END
DMA End Flag
Set when the transfer described by the
current control block is complete. Write
1 to clear.
W1C
0x0
0
ACTIVE
Activate the DMA
This bit enables the DMA. The DMA will
start if this bit is set and the CB_ADDR is
non zero. The DMA transfer can be
paused and resumed by clearing, then
setting it again.
This bit is automatically cleared at the
end of the complete DMA transfer, ie.
after a NEXTCONBK = 0x0000_0000 has
been loaded.
RW
0x0
0_CONBLK_AD 1_CONBLK_AD 2_CONBLK_
AD 3_CONBLK_AD 4_CONBLK_AD 5_CONBLK_AD
6_CONBLK_AD 7_CONBLK_AD 8_CONBLK_AD 9_CONBLK_AD 10_CONBLK_AD 11_CONBLK_AD
12_CONBLK_AD 13_CONBLK_AD 14_CONBLK_AD Register
Synopsis
DMA Control Block Address register.
Bit(s)
Field Name
Description
Type
Reset
31:0
SCB_ADDR
Control Block Address
This tells the DMA where to find a Control Block
stored in memory. When the ACTIVE bit is set and this
address is non zero, the DMA will begin its transfer by
loading the contents of the addressed CB into the
relevant DMA channel registers.
At the end of the transfer this register will be updated
with the ADDR field of the NEXTCONBK control block
register. If this field is zero, the DMA will stop.
Reading this register will return the address of the
currently active CB (in the linked list of CB s). The
address must be 256 bit aligned, so the bottom 5 bits
of the address must be zero.
RW
0x0
0_TI 1_TI 2_TI 3_TI 4_TI 5_TI 6_TI Register
Synopsis
DMA Transfer Information.
Bit(s)
Field Name
Description
Type
Reset