Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 41
© 2012 Broadcom Corporation. All rights reserved
Most of the control block registers cannot be written to directly as they loaded automatically
from memory. They can be read to provide status information, and to indicate the progress of
the current DMA transfer. The value loaded into the NEXTCONBK register can be
overwritten so that the linked list of Control Block data structures can be dynamically altered.
However it is only safe to do this when the DMA is paused.
4.2.1.2 Register Map
DMA Address Map
Address
Offset
Register Name Description Size
0x0
0_CS
DMA Channel 0 Control and Status
32
0x4
0_CONBLK_AD
DMA Channel 0 Control Block Address
32
0x8
0_TI
DMA Channel 0 CB Word 0 (Transfer Information)
32
0xc
0_SOURCE_AD
DMA Channel 0 CB Word 1 (Source Address)
32
0x10
0_DEST_AD
DMA Channel 0 CB Word 2 (Destination Address)
32
0x14
0_TXFR_LEN
DMA
Channel 0 CB Word 3 (Transfer Length)
32
0x18
0_STRIDE
DMA Channel 0 CB Word 4 (2D Stride)
32
0x1c
0_NEXTCONBK
DMA Channel 0 CB Word 5 (Next CB Address)
32
0x20
0_DEBUG
DMA Channel 0 Debug
32
0x100
1_CS
DMA Channel 1 Control and Status
32
0x104
1_CONBLK_AD
DMA Channel 1 Control Block Address
32
0x108
1_TI
DMA Channel 1 CB Word 0 (Transfer Information)
32
0x10c
1_SOURCE_AD
DMA Channel 1 CB Word 1 (Source Address)
32
0x110
1_DEST_AD
DMA Channel 1 CB
Word 2 (Destination Address)
32
0x114
1_TXFR_LEN
DMA Channel 1 CB Word 3 (Transfer Length)
32