Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 38

4 DMA Controller

4.1 Overview

The majority of hardware pipelines and peripherals within the BCM2835 are bus masters,

enabling them to efficiently satisfy their own data requirements. This reduces the

requirements of the DMA controller to block-to-block memory transfers and supporting some

of the simpler peripherals. In addition, the DMA controller provides a read only prefetch

mode to allow data to be brought into the L2 cache in anticipation of its later use.

Beware that the DMA controller is direcly connected to the peripherals. Thus the DMA

controller must be set-up to use the Physical (harware) addresses of the peripherals.

The BCM2835 DMA Controller provides a total of 16 DMA channels. Each channel operates

independently from the others and is internally arbitrated onto one of the 3 system busses.

This means that the amount of bandwidth that a DMA channel may consume can be

controlled by the arbiter settings.

Each DMA channel operates by loading a Control Block (CB) data structure from memory

into internal registers. The Control Block defines the required DMA operation. Each Control

Block can point to a further Control Block to be loaded and executed once the operation

described in the current Control Block has completed. In this way a linked list of Control

Blocks can be constructed in order to execute a sequence of DMA operations without

software intervention.

The DMA supports AXI read bursts to ensure efficient external SDRAM use. The DMA

control block contains a burst parameter which indicates the required burst size of certain

memory transfers. In general the DMA doesn’t do write bursts, although wide writes will be

done in 2 beat bursts if possible.

Memory-to-Peripheral transfers can be paced by a Data Request (DREQ) signal which is

generated by the peripheral. The DREQ signal is level sensitive and controls the DMA by

gating its AXI bus requests.

A peripheral can also provide a Panic signal alongside the DREQ to indicate that there is an

imminent danger of FIFO underflow or overflow or similar critical situation. The Panic is

used to select the AXI apriority level which is then passed out onto the AXI bus so that it can

be used to influence arbitration in the rest of the system.

The allocation of peripherals to DMA channels is programmable.

The DMA can deal with byte aligned transfers and will minimise bus traffic by buffering and

packing misaligned accesses.

Each DMA channel can be fully disabled via a top level power register to save power.