Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 29
© 2012 Broadcom Corporation. All rights reserved
0x1c
CLKT
Clock Stretch Timeout 32
C Register
Synopsis
The control register is used to enable interrupts, clear the FIFO, define a read or write
operation and start a transfer.
The READ field specifies the type of transfer.
The CLEAR field is used to clear the FIFO. Writing to this field is a one-shot operation
which will always read back as zero. The CLEAR bit can set at the same time as the
start transfer bit, and will result in the FIFO being cleared just prior to the start of
transfer. Note that clearing the FIFO during a transfer will result in the transfer being
aborted.
The ST field starts a new BSC transfer. This has a one shot action, and so the bit will
always read back as 0 .
The INTD field enables interrupts at the end of a transfer the DONE condition. The
interrupt remains active until the DONE condition is cleared by writing a 1 to the
I2CS.DONE field. Writing a 0 to the INTD field disables interrupts on DONE.
The INTT field enables interrupts whenever the FIFO is or more empty and needs
writing (i.e. during a write transfer) - the TXW condition. The interrupt remains active
until the TXW condition is cleared by writing sufficient data to the FIFO to complete the
transfer. Writing a 0 to the INTT field disables interrupts on TXW.
The INTR field enables interrupts whenever the FIFO is or more full and needs reading
(i.e. during a read transfer) - the RXR condition. The interrupt remains active until the
RXW condition is cleared by reading sufficient data from the RX FIFO. Writing a 0 to
the INTR field disables interrupts on RXR.
The I2CEN field enables BSC operations. If this bit is 0 then transfers will not be
performed. All register accesses are still permitted however.
Bit(s)
Field Name
Description
Type
Reset
31:16
Reserved
-
Write as 0, read as don't care
15 I2CEN I2C Enable
0 = BSC controller is disabled
1 = BSC controller is enabled
RW 0x0
14:11
Reserved
-
Write as 0, read as don't care
10 INTR INTR Interrupt on RX
0 = Don t generate interrupts on RXR condition.
1 = Generate interrupt while RXR = 1.
RW 0x0
9 INTT INTT Interrupt on TX
0 = Don t generate interrupts on TXW condition.
1 = Generate interrupt while TXW = 1.
RW 0x0