Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 27
© 2012 Broadcom Corporation. All rights reserved
AUXSPI0/1_TXHOLD Register
(0x7E21 50B0-0x7E21 50BC
0x7E21 50F0-0x7E21 50FC)
S
YNOPSIS The AUXSPIx_TXHOLD registers are the extended CS port of the SPI interfaces
These four addresses all write to the same FIFO.
Writing to these addresses causes the SPI CS_n pins to remain asserted at the
end of the access
Bit(s) Field Name Description Type Reset
31:16
- Reserved, write zero, read as don’t care
15:0 Data
Writes to this address range end up in the transmit
FIFO. Data is lost when writing whilst the transmit
FIFO is full.
Reads from this address will take the top entry from
the receive FIFO. Reading whilst the receive FIFO is
will return the last data received.
R/W 0