Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 26
© 2012 Broadcom Corporation. All rights reserved
Busy
This status bit indicates if the module is busy. It will be clear when the TX FIFO is empty
and the module has finished all activities, including waiting the minimum CS high time.
AUXSPI0/1_PEEK Register (0x7E21 508C,0x7E21 50CC)
S
YNOPSIS The AUXSPIx_PEEK registers show received data of the SPI interfaces.
Bit(s) Field Name Description Type Reset
31:16
- Reserved, write zero, read as don’t care
15:0 Data
Reads from this address will show the top entry from
the receive FIFO, but the data is not taken from the
FIFO. This provides a means of inspecting the data
but not removing it from the FIFO.
RO 0
AUXSPI0/1_IO Register
(0x7E21 50A0-0x7E21 50AC
0x7E21 50E0-0x7E21 50EC)
S
YNOPSIS The AUXSPIx_IO registers are the primary data port of the SPI interfaces
These four addresses all write to the same FIFO.
Writing to any of these addresses causes the SPI CS_n pins to be de-asserted at
the end of the access
Bit(s) Field Name Description Type Reset
31:16
- Reserved, write zero, read as don’t care
15:0 Data
Writes to this address range end up in the transmit
FIFO. Data is lost when writing whilst the transmit
FIFO is full.
Reads from this address will take the top entry from
the receive FIFO. Reading whilst the receive FIFO is
will return the last data received.
R/W 0