Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 25
© 2012 Broadcom Corporation. All rights reserved
CS high time
The SPI CS will always be high for at least 1 SPI clock cycle. Some SPI devices need more
time to process the data. This field will set a longer CS-high time. So the actual CS high time
is (CS_high_time + 1) (In SPI clock cycles).
Interrupts
The SPI block has two interrupts: TX FIFO is empty, SPI is Idle.
TX FIFO is empty:
This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO.
At that time the interface will still be busy shifting out that data. This also implies that the
receive FIFO will not yet contain the last received data.
It is possible at that time to fill the TX FIFO again and read the receive FIFO entries which
have been received. There is a RX FIFO level field which tells exactly how many words are
in the receive FIFO. In general at that time the receive FIFO should contain the number of
Tx items minus one (the last one still being received). Note that there is no "receive FIFO
full" interrupt or "receive FIFO overflow" flag as the number of entries received can never
be more then the number of entries transmitted.
AUX is IDLE:
This interrupt will be asserted when the module has finished all activities, including waiting
the minimum CS high time. This guarantees that any receive data will be available and
`transparent' changes can be made to the configuration register (e.g. inverting the SPI clock
polarity).
AUXSPI0/1_STAT Register (0x7E21 5088,0x7E21 50C8)
S
YNOPSIS The AUXSPIx_STAT registers show the status of the SPI interfaces.
Bit(s) Field Name Description Type Reset
31:24
TX FIFO level The number of data units in the transmit data FIFO R/W 0
23:12
RX FIFO level The number of data units in the receive data FIFO. R/W 0
11:5
- Reserved, write zero, read as don’t care
4
TX Full If 1 the transmit FIFO is full
If 0 the transmit FIFO can accept at least 1 data unit.
R/W 0
3
TX Empty If 1 the transmit FIFO is empty
If 0 the transmit FIFO holds at least 1 data unit.
R/W 0
2
RX Empty If 1 the receiver FIFO is empty
If 0 the receiver FIFO holds at least 1 data unit.
R/W 0
6
Busy Indicates the module is busy transferring data. R/W 0
5:0 Bit count
The number of bits still to be processed. Starts with
'shift-length' and counts down.
R/W 0