Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 200
© 2012 Broadcom Corporation. All rights reserved
15 USB
The USB core used in the Videocore is build from Synopsys IP. Details about the block can be found in
DWC_otg_databook.pdf (Which can also be downloaded from
https://www.synopsys.com/dw/ipdir.php?ds=dwc_usb_2_0_hs_otg ) .
15.1 Configuration
A number of features of the block are specified before the block is build and thus can not be
changed using software. The above mentioned document has a list of these under the chapter
"Configuration Parameters". The following table list all configuration parameters mentioned in
that chapter and the values which have been chosen.
Feature/Parameter
Selected value
Mode of Operation
0: HNP
-
and SRP
-
Capable OTG (Device and
Host)
LPM Mode of Operation
0: Non
-
LPM
-
capable core
HSIC Mode of Operation
0:
Non
-
HSIC
-
capable core
Architecture
2: Internal DMA
Point
-
to
-
Point Application Only
0: No
High
-
Speed PHY Interfaces
1: UTMI+
USB 1.1 Full
-
Speed Serial Transceiver Interface
1: Dedicated FS
USB IC_USB Transceiver Interface
0: Non
-
IC_USB
-
capable
Default (Power on) Interface selection: FS_USB/IC_USB
0 : FS_USB interface
Data Width of the UTMI+ Interface
0: 8 bits
Enable I2C Interface
0: None
Enable ULPI Carkit
0: No
Enable PHY Vendor Control Interface
0: No