Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 199

The pre-divider register is 10 bits wide and can be written or read from. This register has been added

as the SP804 expects a 1MHz clock which we do not have. Instead the pre-divider takes the APB

clock and divides it down according to:

timer_clock = apb_clock/(pre_divider+1)

The reset value of this register is 0x7D so gives a divide by 126.

Free running counter

Name: Free running

Address: base + 0x420

Reset: 0x000

Bit(s)

R/W

Function

31:0

Counter value

The free running counter is not present in the SP804.

The free running counter is a 32 bits wide read only register. The register is enabled by setting bit 9

of the Timer control register. The free running counter is incremented immediately after it is

enabled. The timer can not be reset but when enabled, will always increment and roll-over. The free

running counter is also running from the APB clock and has its own clock pre-divider controlled by

bits 16-23 of the timer control register.

This register will be halted too if bit 8 of the control register is set and the ARM is in Debug Halt

mode.