Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 198
© 2012 Broadcom Corporation. All rights reserved
Timer IRQ clear register:
The timer IRQ clear register is write only. When writing this register the interrupt-pending bit is
cleared.
When reading this register it returns 0x544D5241 which is the ASCII reversed value for "ARMT".
Timer Raw IRQ register
The raw IRQ register is a read-only register. It shows the status of the interrupt pending bit.
Name: Raw IRQ
Address: base + 0x40C
Reset: 0x3E0020
Bit(s)
R/W
Function
31:0
R
0
0
R
0 : The interrupt pending bits is clear
1 : The interrupt pending bit is set.
The interrupt pending bits is set each time the value register is counted down to zero. The interrupt
pending bit can not by itself generates interrupts. Interrupts can only be generated if the interrupt
enable bit is set.
Timer Masked IRQ register:
The masked IRQ register is a read-only register. It shows the status of the interrupt signal. It is simply
a logical AND of the interrupt pending bit and the interrupt enable bit.
Name: Masked IRQ
Address: base + 0x40C
Reset: 0x3E0020
Bit(s)
R/W
Function
31:0
R
0
0
R
0 :
Interrupt line not asserted.
1 :Interrupt line is asserted, (the interrupt pending and the interrupt
enable bit are set.)
Timer Reload register:
This register is a copy of the timer load register. The difference is that a write to this register does
not trigger an immediate reload of the timer value register. Instead the timer load register value is
only accessed if the value register has finished counting down to zero.
The timer pre-divider register:
Name: pre
-
divide
Address: base + 0x41C
Reset: 0x07D
Bit(s)
R/W
Function
31:10
-
<Unused>
9:0
R/W
Pre
-
divider value.
The Pre-divider register is not present in the SP804.