Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 193
© 2012 Broadcom Corporation. All rights reserved
DMACR Register
Synopsis
This is the disabled DMA Control Register, writing to it has not effect and
reading returns 0.
Bit(s)
Field Name
Description
Type
Reset
31:3
Reserved
-
Write as 0, read as don't care
2 DMAONERR Unsupported, write zero, read as don't care RW 0x0
1 TXDMAE Unsupported, write zero, read as don't care RW 0x0
0 RXDMAE Unsupported, write zero, read as don't care RW 0x0
ITCR Register
Synopsis
This is the Test Control Register UART_ITCR.
Bit(s)
Field Name
Description
Type
Reset
31:2
Reserved
-
Write as 0, read as don't care
1 ITCR1 Test FIFO enable. When this bit it 1, a write
to the Test Data Register, UART_DR writes
data into the receive FIFO, and reads from
the UART_DR register reads data out of
the transmit FIFO.
When this bit is 0, data cannot be read
directly from the transmit FIFO or written
directly to the receive FIFO (normal
operation).
RW 0x0
0 ITCR0 Integration test enable. When this bit is 1,
the UART is placed in integration test
mode, otherwise it is in normal operation.
RW 0x0