Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 192
© 2012 Broadcom Corporation. All rights reserved
ICR Register
Synopsis
The UART_ICR Register is the interrupt clear register.
Bit(s)
Field Name
Description
Type
Reset
31:11
Reserved
-
Write as 0, read as don't care
10 OEIC Overrun error interrupt clear. Clears the
UARTOEINTR interrupt.
RW 0x0
9 BEIC Break error interrupt clear. Clears the
UARTBEINTR interrupt.
RW 0x0
8 PEIC Parity error interrupt clear. Clears the
UARTPEINTR interrupt.
RW 0x0
7 FEIC Framing error interrupt clear. Clears the
UARTFEINTR interrupt..
RW 0x0
6 RTIC Receive timeout interrupt clear. Clears the
UARTRTINTR interrupt.
RW 0x0
5 TXIC Transmit interrupt clear. Clears the
UARTTXINTR interrupt.
RW 0x0
4 RXIC Receive masked interrupt status. Returns
the masked interrupt state of the
UARTRXINTR interrupt.
RW 0x0
3 DSRMIC Unsupported, write zero, read as don't care RW 0x0
2 DCDMIC Unsupported, write zero, read as don't care RW 0x0
1 CTSMIC nUARTCTS modem masked interrupt
status. Returns the masked interrupt state
of the UARTCTSINTR interrupt.
RW 0x0
0 RIMIC Unsupported, write zero, read as don't care RW 0x0