Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 191
© 2012 Broadcom Corporation. All rights reserved
Synopsis
The UART_MIS Register is the masked interrupt status register. This register
returns the current masked status value of the corresponding interrupt.
NOTE: All the bits, except for the modem status interrupt bits (bits 3 to 0), are
cleared to 0 when reset. The modem status interrupt bits are undefined after
reset.
Bit(s)
Field Name
Description
Type
Reset
31:11
Reserved
-
Write as 0, read as don't care
10 OEMIS Overrun error masked interrupt status.
Returns the masked interrupt state of the
UARTOEINTR interrupt.
RW 0x0
9 BEMIS Break error masked interrupt status.
Returns the masked interrupt state of the
UARTBEINTR interrupt.
RW 0x0
8 PEMIS Parity error masked interrupt status.
Returns the masked interrupt state of the
UARTPEINTR interrupt.
RW 0x0
7 FEMIS Framing error masked interrupt status.
Returns the masked interrupt state of the
UARTFEINTR interrupt.
RW 0x0
6 RTMIS Receive timeout masked interrupt status.
Returns the masked interrupt state of the
UARTRTINTR interrupt.
RW 0x0
5 TXMIS Transmit masked interrupt status. Returns
the masked interrupt state of the
UARTTXINTR interrupt.
RW 0x0
4 RXMIS Receive masked interrupt status. Returns
the masked interrupt state of the
UARTRXINTR interrupt.
RW 0x0
3 DSRMMIS Unsupported, write zero, read as don't care RW 0x0
2 DCDMMIS Unsupported, write zero, read as don't care RW 0x0
1 CTSMMIS nUARTCTS modem masked interrupt
status. Returns the masked interrupt state
of the UARTCTSINTR interrupt.
RW 0x0
0 RIMMIS Unsupported, write zero, read as don't care RW 0x0