Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 189
© 2012 Broadcom Corporation. All rights reserved
6 RTIM Receive timeout interrupt mask. A read
returns the current mask for the
UARTRTINTR interrupt. On a write of 1, the
mask of the interrupt is set. A write of 0
clears the mask.
RW 0x0
5 TXIM Transmit interrupt mask. A read returns the
current mask for the UARTTXINTR
interrupt. On a write of 1, the mask of the
interrupt is set. A write of 0 clears the mask.
RW 0x0
4 RXIM Receive interrupt mask. A read returns the
current mask for the UARTRXINTR
interrupt. On a write of 1, the mask of the
interrupt is set. A write of 0 clears the mask.
RW 0x0
3 DSRMIM Unsupported, write zero, read as don't care RO 0x0
2 DCDMIM Unsupported, write zero, read as don't care RO 0x0
1 CTSMIM nUARTCTS modem interrupt mask. A read
returns the current mask for the
UARTCTSINTR interrupt. On a write of 1,
the mask of the interrupt is set. A write of 0
clears the mask.
RW 0x0
0 RIMIM Unsupported, write zero, read as don't care RO 0x0
RIS Register
Synopsis
The UART_RIS Register is the raw interrupt status register. It is a read-only
register. This register returns the current raw status value, prior to masking, of
the corresponding interrupt.
NOTE: All the bits, except for the modem status interrupt bits (bits 3 to 0), are
cleared to 0 when reset. The modem status interrupt bits are undefined after
reset.
Bit(s)
Field Name
Description
Type
Reset
31:11
Reserved
-
Write as 0, read as don't care