Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 188
© 2012 Broadcom Corporation. All rights reserved
2:0 TXIFLSEL Transmit interrupt FIFO level select. The
trigger points for the transmit interrupt are
as follows:
b000 = Transmit FIFO becomes 1/8 full
b001 = Transmit FIFO becomes 1/4 full
b010 = Transmit FIFO becomes 1/2 full
b011 = Transmit FIFO becomes 3/4 full
b100 = Transmit FIFO becomes 7/8 full
b101-b111 = reserved.
RW 0x0
IMSC Register
Synopsis
The UART_IMSC Register is the interrupt mask set/clear register. It is a
read/write register. On a read this register returns the current value of the
mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the
corresponding mask of that interrupt. A write of 0 clears the corresponding
mask.
Bit(s)
Field Name
Description
Type
Reset
31:11
Reserved
-
Write as 0, read as don't care
10 OEIM Overrun error interrupt mask. A read
returns the current mask for the interrupt.
On a write of 1, the mask of the
UARTOEINTR interrupt is set. A write of 0
clears the mask.
RW 0x0
9 BEIM Break error interrupt mask. A read returns
the current mask for the UARTBEINTR
interrupt. On a write of 1, the mask of the
interrupt is set. A write of 0 clears the mask.
RW 0x0
8 PEIM Parity error interrupt mask. A read returns
the current mask for the UARTPEINTR
interrupt. On a write of 1, the mask of the
interrupt is set. A write of 0 clears the mask.
RW 0x0
7 FEIM Framing error interrupt mask. A read
returns the current mask for the
UARTFEINTR interrupt. On a write of 1, the
mask of the interrupt is set. A write of 0
clears the mask.
RW 0x0