Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 187
© 2012 Broadcom Corporation. All rights reserved
6:3
Reserved
-
Write as 0, read as don't care
2 SIRLP Unsupported, write zero, read as don't care RO 0x0
1 SIREN Unsupported, write zero, read as don't care RO 0x0
0 UARTEN UART enable:
0 = UART is disabled. If the UART is
disabled in the middle of transmission or
reception, it completes the current
character before stopping.
1 = the UART is enabled.
RW 0x0
IFLS Register
Synopsis
The UART_IFLS Register is the interrupt FIFO level select register. You can
use this register to define the FIFO level that triggers the assertion of the
combined interrupt signal.
The interrupts are generated based on a transition through a level rather than
being based on the level. That is, the interrupts are generated when the fill
level progresses through the trigger level.
The bits are reset so that the trigger level is when the FIFOs are at the half-
way mark.
Bit(s)
Field Name
Description
Type
Reset
31:12
Reserved
-
Write as 0, read as don't care
11:9 RXIFPSEL Unsupported, write zero, read as don't care RO 0x0
8:6 TXIFPSEL Unsupported, write zero, read as don't care RO 0x0
5:3 RXIFLSEL Receive interrupt FIFO level select. The
trigger points for the receive interrupt are as
follows:
b000 = Receive FIFO becomes 1/8 full
b001 = Receive FIFO becomes 1/4 full
b010 = Receive FIFO becomes 1/2 full
b011 = Receive FIFO becomes 3/4 full
b100 = Receive FIFO becomes 7/8 full
b101-b111 = reserved.
RW 0x0