Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 186
© 2012 Broadcom Corporation. All rights reserved
Bit(s)
Field Name
Description
Type
Reset
31:16
Reserved
-
Write as 0, read as don't care
15 CTSEN CTS hardware flow control enable. If this bit
is set to 1, CTS hardware flow control is
enabled. Data is only transmitted when the
nUARTCTS signal is asserted.
RW 0x0
14 RTSEN RTS hardware flow control enable. If this bit
is set to 1, RTS hardware flow control is
enabled. Data
is only requested when there is space in
the receive FIFO for it to be received.
RW 0x0
13 OUT2 Unsupported, write zero, read as don't care RO 0x0
12 OUT1 Unsupported, write zero, read as don't care RO 0x0
11 RTS Request to send. This bit is the
complement of the UART request to send,
nUARTRTS, modem status output. That is,
when the bit is programmed to a 1 then
nUARTRTS is LOW.
RW 0x0
10 DTR Unsupported, write zero, read as don't care RO 0x0
9 RXE Receive enable. If this bit is set to 1, the
receive section of the UART is enabled.
Data reception occurs for UART signals.
When the UART is disabled in the middle of
reception, it completes the current
character before stopping.
RW 0x1
8 TXE Transmit enable. If this bit is set to 1, the
transmit section of the UART is enabled.
Data transmission occurs for UART signals.
When the UART is disabled in the middle of
transmission, it completes the current
character before stopping.
RW 0x1
7 LBE Loopback enable. If this bit is set to 1, the
UARTTXD path is fed through to the
UARTRXD path. In UART mode, when this
bit is set, the modem outputs are also fed
through to the modem inputs. This bit is
cleared to 0 on reset, to disable loopback.
RW 0x0