Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 184
© 2012 Broadcom Corporation. All rights reserved
Bit(s)
Field Name
Description
Type
Reset
31:6
Reserved
-
Write as 0, read as don't care
5:0 FBRD The fractional baud rate divisor. RW 0x0
LCRH Register
Synopsis
The UARTLCR_ LCRH Register is the line control register.
NOTE: The UART_LCRH, UART_IBRD, and UART_FBRD registers must not
be changed:
when the UART is enabled
when completing a transmission or a reception when it has been programmed
to become disabled.
Bit(s
)
Field Name
Description
Type
Reset
31:8
Reserved
-
Write as 0, read as don't care
7 SPS Stick parity select.
0 = stick parity is disabled
1 = either:
if the EPS bit is 0 then the parity bit is
transmitted and checked as a 1
if the EPS bit is 1 then the parity bit is
transmitted and checked as a 0. See Table
25 9.
RO 0x0
6:5 WLEN Word length. These bits indicate the
number of data bits transmitted or received
in a frame as follows:
b11 = 8 bits
b10 = 7 bits
b01 = 6 bits
b00 = 5 bits.
RW 0x0
4 FEN Enable FIFOs:
0 = FIFOs are disabled (character mode)
that is, the FIFOs become 1-byte-deep
holding registers
1 = transmit and receive FIFO buffers are
enabled (FIFO mode).
RW 0x0