Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 182
© 2012 Broadcom Corporation. All rights reserved
7 TXFE Transmit FIFO empty. The meaning of this
bit depends on the state of the FEN bit in
the Line Control Register, UARTLCR_
LCRH.
If the FIFO is disabled, this bit is set when
the transmit holding register is empty.
If the FIFO is enabled, the TXFE bit is set
when the transmit FIFO is empty. This bit
does not indicate if there is data in the
transmit shift register.
RW 0x1
6 RXFF Receive FIFO full. The meaning of this bit
depends on the state of the FEN bit in the
UARTLCR_ LCRH Register.
If the FIFO is disabled, this bit is set when
the receive holding register is full.
If the FIFO is enabled, the RXFF bit is set
when the receive FIFO is full.
RW 0x0
5 TXFF Transmit FIFO full. The meaning of this bit
depends on the state of the FEN bit in the
UARTLCR_ LCRH Register.
If the FIFO is disabled, this bit is set when
the transmit holding register is full.
If the FIFO is enabled, the TXFF bit is set
when the transmit FIFO is full.
RW 0x0
4 RXFE Receive FIFO empty. The meaning of this
bit depends on the state of the FEN bit in
the UARTLCR_H
Register.
If the FIFO is disabled, this bit is set when
the receive holding register is empty.
If the FIFO is enabled, the RXFE bit is set
when the receive FIFO is empty.
RW 0x0
3 BUSY UART busy. If this bit is set to 1, the UART
is busy transmitting data. This bit remains
set until the complete byte, including all the
stop bits, has been sent from the shift
register.
This bit is set as soon as the transmit FIFO
becomes non-empty, regardless of whether
the UART is
enabled or not.
RW 0x0
2 DCD Unsupported, write zero, read as don't care RW 0x0
1 DSR Unsupported, write zero, read as don't care RW 0x0