Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 181
© 2012 Broadcom Corporation. All rights reserved
2 BE Break error. This bit is set to 1 if a break
condition was detected, indicating that the
received data input
was held LOW for longer than a full-word
transmission time (defined as start, data,
parity and stop
bits).
In FIFO mode, this error is associated with
the character at the top of the FIFO. When
a break occurs,
only one 0 character is loaded into the
FIFO. The next character is only enabled
after the receive data
input goes to a 1 (marking state), and the
next valid start bit is received.
RW 0x0
1 PE Parity error. When set to 1, it indicates that
the parity of the received data character
does not match the
parity that the EPS and SPS bits in the Line
Control Register, UART_LCRH select. In
FIFO mode, this error is associated with the
character at the top of the FIFO.
RW 0x0
0 FE Framing error. When set to 1, it indicates
that the received character did not have a
valid stop bit (a valid
stop bit is 1). In FIFO mode, this error is
associated with the character at the top of
the FIFO.
RW 0x0
FR Register
Synopsis
The UART_FR Register is the flag register.
Bit(s)
Field Name
Description
Type
Reset
31:9
Reserved
-
Write as 0, read as don't care
8 RI Unsupported, write zero, read as don't care RW 0x0