Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 180
© 2012 Broadcom Corporation. All rights reserved
8 FE Framing error. When set to 1, it indicates
that the received character did not have a
valid stop bit (a valid
stop bit is 1). In FIFO mode, this error is
associated with the character at the top of
the FIFO.
RW 0x0
7:0 DATA Receive (read) data character.
Transmit (write) data character.
RW 0x0
RSRECR Register
Synopsis
The UART_RSRECR Register is the receive status register/error clear
register. If the status is read from this register, then the status information for
break, framing and parity corresponds to the data character read from the
Data Register, UART_DR. The status information for overrun is set
immediately when an overrun condition occurs. NOTE: The received data
character must be read first from the Data Register, UART_DR on before
reading the error status associated with that data character from this register.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3 OE Overrun error. This bit is set to 1 if data is
received and the receive FIFO is already
full.
This is cleared to 0 once there is an empty
space in the FIFO and a new character can
be written to it.
RW 0x0