Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 18
© 2012 Broadcom Corporation. All rights reserved
AUX_MU_STAT_REG Register (0x7E21 5064)
S
YNOPSIS The AUX_MU_STAT_REG provides a lot of useful information about the internal status of
the mini UART not found on a normal 16550 UART.
Bit(s) Field Name Description Type Reset
31:28
Reserved, write zero, read as don’t care
27:24
Transmit
FIFO fill level
These bits shows how many symbols are stored in the
transmit FIFO
The value is in the range 0-8
R 0
23:20
Reserved, write zero, read as don’t care
19:16
Receive FIFO
fill level
These bits shows how many symbols are stored in the
receive FIFO
The value is in the range 0-8
R 0
15:10
Reserved, write zero, read as don’t care
9
Transmitter
done
This bit is set if the transmitter is idle and the transmit
FIFO is empty.
It is a logic AND of bits 2 and 8
R 1
8
Transmit
FIFO is empty
If this bit is set the transmitter FIFO is empty. Thus it
can accept 8 symbols.
R 1
7 CTS line This bit shows the status of the UART1_CTS line. R 0
6 RTS status This bit shows the status of the UART1_RTS line. R 0
5
Transmit
FIFO is full
This is the inverse of bit 1 R 0
4
Receiver
overrun
This bit is set if there was a receiver overrun. That is:
one or more characters arrived whilst the receive
FIFO was full. The newly arrived characters have
been discarded. This bit is cleared each time the
AUX_MU_LSR_REG register is read.
R 0
3
Transmitter is
idle
If this bit is set the transmitter is idle.
If this bit is clear the transmitter is idle.
R 1
2
Receiver is
idle
If this bit is set the receiver is idle.
If this bit is clear the receiver is busy.
This bit can change unless the receiver is disabled
R 1
1
Space
available
If this bit is set the mini UART transmitter FIFO can
accept at least one more symbol.
If this bit is clear the mini UART transmitter FIFO is
full
R 0