Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 179
© 2012 Broadcom Corporation. All rights reserved
Synopsis
The UART_DR Register is the data register. For words to be transmitted:
if the FIFOs are enabled, data written to this location is pushed onto the
transmit FIFO.
if the FIFOs are not enabled, data is stored in the transmitter holding register
(the bottom word of the transmit FIFO).
The write operation initiates transmission from the UART. The data is prefixed
with a start bit, appended with the appropriate parity bit (if parity is enabled),
and a stop bit. The resultant word is then transmitted.
For received words:
if the FIFOs are enabled, the data byte and the 4-bit status (break, frame,
parity, and overrun) is pushed onto the 12-bit wide receive FIFO
if the FIFOs are not enabled, the data byte and status are stored in the
receiving holding register (the bottom word of the receive FIFO).
Bit(s)
Field Name
Description
Type
Reset
31:12
Reserved
-
Write as 0, read as don't care
11 OE Overrun error. This bit is set to 1 if data is
received and the receive FIFO is already
full.
This is cleared to 0 once there is an empty
space in the FIFO and a new character can
be written to it.
RW 0x0
10 BE Break error. This bit is set to 1 if a break
condition was detected, indicating that the
received data input
was held LOW for longer than a full-word
transmission time (defined as start, data,
parity and stop
bits).
In FIFO mode, this error is associated with
the character at the top of the FIFO. When
a break occurs,
only one 0 character is loaded into the
FIFO. The next character is only enabled
after the receive data
input goes to a 1 (marking state), and the
next valid start bit is received.
RW 0x0
9 PE Parity error. When set to 1, it indicates that
the parity of the received data character
does not match the
parity that the EPS and SPS bits in the Line
Control Register, UART_LCRH select. In
FIFO mode, this error is associated with the
character at the top of the FIFO.
RW 0x0