Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 177

— UARTOEINTR, because of an overrun error

— UARTBEINTR, because of a break in the reception

— UARTPEINTR, because of a parity error in the received character

— UARTFEINTR, because of a framing error in the received character.

One can enable or disable the individual interrupts by changing the mask bits in the Interrupt

Mask Set/Clear Register, UART_IMSC. Setting the appropriate mask bit HIGH enables the

interrupt.

UARTRXINTR:

The transmit interrupt changes state when one of the following events occurs:

• If the FIFOs are enabled and the transmit FIFO is equal to or lower than the

programmed trigger level then the transmit interrupt is asserted HIGH. The transmit

interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the

trigger level, or by clearing the interrupt.

• If the FIFOs are disabled (have a depth of one location) and there is no data present in

the transmitters single location, the transmit interrupt is asserted HIGH. It is cleared by

performing a single write to the transmit FIFO, or by clearing the interrupt.

UARTRTINTR:

The receive interrupt changes state when one of the following events occurs:

• If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level.

When this happens, the receive interrupt is asserted HIGH. The receive interrupt is

cleared by reading data from the receive FIFO until it becomes less than the trigger level,

or by clearing the interrupt.

• If the FIFOs are disabled (have a depth of one location) and data is received thereby

filling the location, the receive interrupt is asserted HIGH. The receive interrupt is cleared

by performing a single read of the receive FIFO, or by clearing the interrupt.

13.4 Register View

The PL011 USRT is mapped on base adderss 0x7E20100. It has the following memory-

mapped registers.

UART Address Map

Address

Offset

0x0 DR Data Register 32

0x4 RSRECR 32

0x18 FR Flag register 32