Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 174
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C0 C1 C2 C3 Register
Synopsis
System Timer Compare.
The system timer compare registers hold the compare value for each of the four timer channels.
Whenever the lower 32-bits of the free-running counter matches one of the compare values the
corresponding bit in the system timer control/status register is set.
Each timer peripheral (minirun and run) has a set of four compare registers.
Bit(s)
Field Name
Description
Type
Reset
31:0
CMP
Compare value for match channel n.
RW
0x0