Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 173
© 2012 Broadcom Corporation. All rights reserved
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3
M3
System Timer Match 3
0 = No Timer 3 match since last cleared.
1 = Timer 3 match detected.
RW
0x0
2
M2
System Timer Match 2
0 = No Timer 2 match since last cleared.
1 = Timer 2 match detected.
RW
0x0
1
M1
System Timer Match 1
0 = No Timer 1 match since last cleared.
1 = Timer 1 match detected.
RW
0x0
0
M0
System Timer Match 0
0 = No Timer 0 match since last cleared.
1 = Timer 0 match detected.
RW
0x0
CLO Register
Synopsis
System Timer Counter Lower bits.
The system timer free-running counter lower register is a read-only register that returns the current value
of the lower 32-bits of the free running counter.
Bit(s)
Field Name
Description
Type
Reset
31:0
CNT
Lower 32
-
bits of the free running counter value.
RW
0x0
CHI Register
Synopsis
System Timer Counter Higher bits.
The system timer free-running counter higher register is a read-only register that returns the current value
of the higher 32-bits of the free running counter.
Bit(s)
Field Name
Description
Type
Reset
31:0
CNT
Higher 32
-
bits of the free running counter value.
RW
0x0