Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 169
© 2012 Broadcom Corporation. All rights reserved
ICR Register
Synopsis
The Interrupt Clear Register.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3 OEIC Overrun error interrupt clear. Clears the OEINTR
interrupt.
RW 0x0
2 BEIC Break error interrupt clear. Clears the BEINTR
interrupt.
RW 0x0
1 TXIC Transmit interrupt clear. Clears the TXINTR
interrupt.
RW 0x0
0 RXIC Receive masked interrupt status. Returns the
masked interrupt state of the RXINTR interrupt.
RW 0x0
DMACR Register
Synopsis
The DMA Control register is not supported in this version.
Bit(s)
Field Name
Description
Type
Reset
31:3
Reserved
-
Write as 0, read as don't care
2 DMAONERR Unsupported, write zero, read as don't care RW 0x0
1 TXDMAE Unsupported, write zero, read as don't care RW 0x0
0 RXDMAE Unsupported, write zero, read as don't care RW 0x0
TDR Register
Synopsis
The Test Data Register enables data to be written into the receive FIFO and read out
from the transmit FIFO for test purposes.