Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 168
© 2012 Broadcom Corporation. All rights reserved
RIS Register
Synopsis
The Raw Interrupt Status Register returns the current raw status value, prior to
masking, of the corresponding interrupt.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3 OERIS Overrun error interrupt status. Returns the raw
interrupt state of the OEINTR interrupt.
RW 0x0
2 BERIS Break error interrupt status. Returns the raw
interrupt state of the BEINTR interrupt.
RW 0x0
1 TXRIS Transmit interrupt status. Returns the raw
interrupt state of the TXINTR interrupt.
RW 0x0
0 RXRIS Receive interrupt status. Returns the raw
interrupt state of the RXINTR interrupt.
RW 0x0
MIS Register
Synopsis
The Masked Interrupt Status Register returns the current masked status value of the
corresponding interrupt.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3 OEMIS Overrun error masked interrupt status. Returns
the masked interrupt state of the OEINTR
interrupt.
RW 0x0
2 BEMIS Break error masked interrupt status. Returns the
masked interrupt state of the BEINTR interrupt.
RW 0x0
1 TXMIS Transmit masked interrupt status. Returns the
masked interrupt state of the TXINTR interrupt.
RW 0x0
0 RXMIS Receive masked interrupt status. Returns the
masked interrupt state of the RXINTR interrupt.
RW 0x0