Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 167
© 2012 Broadcom Corporation. All rights reserved
5:3 RXIFLSEL RXIFLSEL RX Interrupt FIFO Level Select
Interrupt is triggered when :
000 RX FIFO gets 1/8 full
001 RX FIFO gets 1/4 full
010 RX FIFO gets 1/2 full
011 RX FIFO gets 3/4 full
100 RX FIFO gets 7/8 full
101 111 not used
RW 0x0
2:0 TXIFLSEL TXIFLSEL TX Interrupt FIFO Level Select
Interrupt is triggered when :
000 TX FIFO gets 1/8 full
001 TX FIFO gets 1/4 full
010 TX FIFO gets 1/2 full
011 TX FIFO gets 3/4 full
100 TX FIFO gets 7/8 full
101 111 not used
RW 0x0
IMSC Register
Synopsis
Interrupt Mask Set/Clear Register. On a read this register returns the current value of
the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the
corresponding mask of that interrupt. A write of 0 clears the corresponding mask.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3 OEIM Overrun error interrupt mask. A read returns the
current mask for the interrupt. On a write of 1,
the mask of the OEINTR interrupt is set. A write
of 0 clears the mask.
RW 0x0
2 BEIM Break error interrupt mask. A read returns the
current mask for the BEINTR interrupt. On a
write of 1, the mask of the interrupt is set. A write
of 0 clears the mask.
RW 0x0
1 TXIM Transmit interrupt mask. A read returns the
current mask for the TXINTR interrupt. On a
write of 1, the mask of the interrupt is set. A write
of 0 clears the mask.
RW 0x0
0 RXIM Receive interrupt mask. A read returns the
current mask for the RXINTR interrupt. On a
write of 1, the mask of the interrupt is set. A write
of 0 clears the mask.
RW 0x0