Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 165
© 2012 Broadcom Corporation. All rights reserved
6 ENCTRL ENCTRL ENABLE CONTROL 8bit register
0 = Control register disabled. Implies ordinary
I2C protocol.
1 = Control register enabled. When enabled the
control register is received as a first data
character on the I2C bus.
NOTE: The same behaviour is achieved from the
Host side by using bit SLVADDR[6] of the slave
address.
RO 0x0
5 ENSTAT ENSTAT ENABLE STATUS 8bit register
0 = Status register disabled. Implies ordinary I2C
protocol.
1 = Status register enabled. When enabled the
status register is transferred as a first data
character on the I2C bus. Status register is
transferred to the host.
NOTE: The same behaviour is achieved from the
Host side by using bit SLVADDR[6] of the slave
address.
RW 0x0
4 CPOL CPOL Clock Polarity
0 =
1 = SPI Related
RW 0x0
3 CPHA CPHA Clock Phase
0 =
1 = SPI Related
RW 0x0
2 I2C SPI Mode
0 = Disabled I2C mode
1 = Enabled I2C mode
RW 0x0
1 SPI SPI Mode
0 = Disabled SPI mode
1 = Enabled SPI mode
RW 0x0
0 EN EN Enable Device
1 = Enable I2C SPI Slave.
0 = Disable I2C SPI Slave.
RW 0x0
FR Register
Synopsis
The flag register indicates the current status of the operation.
Bit(s)
Field Name
Description
Type
Reset
31:16
Reserved
-
Write as 0, read as don't care