Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 164
© 2012 Broadcom Corporation. All rights reserved
13 INV_TXF INV-RX Inverse TX status flags
0 = default status flags
When this bit is 0, bit 6 (TXFE - TX FIFO Empty)
will reset to a 1
1 = inverted status flags
When this bit is set, bit 6 (TXFE - TX FIFO Full)
will reset to a 0
* Note: INV_TX bit changes the default values of
6 bit as it is specified for I2C SPI GPU Host
Status Register .
RW 0x0
12 HOSTCTRLEN HOSTCTRLEN Enable Control for Host
0 = Host Control disabled
1 = Host Control enabled
Note: HOSTCTRLEN allows Host to request
GPUSTAT or HCTRL register. The same
behaviour is achieved from the GPU side using
ENSTAT and ENCTRL.
RW 0x0
11 TESTFIFO TESTFIFO TEST FIFO
0 = TESTT FIFO disabled
1 = TESTT FIFO enabled
RW 0x0
10 INV_RXF INV-RX Inverse RX status flags
0 = default status flags
When this bit is 0, bit 6 (RXFF - RX FIFO Full)
will reset to a 0
1 = inverted status flags
When this bit is 0, bit 6 (RXFF - RX FIFO Empty)
will reset to a 1
* NOTE: INV_RX bit changes the default values
of 7 bit as it is specified for I2C SPI GPU Host
Status Register .
RW 0x0
9 RXE RXE Receive Enable
0 = Receive mode disabled
1 = Receive mode enabled
RW 0x0
8 TXE TXE Transmit Enable
0 = Transmit mode disabled
1 = Transmit mode enabled
RW 0x0
7 BRK BRK Break current operation
0 = No effect.
1 = Stop operation and clear the FIFOs.
RW 0x0